What is the change?
Split and redefine the DDR4 device tree nodes, in their respective board
variants so that linker scripts automatically generates a memory section
for each node.

Why do we need this change?
According to the official memory map of Corstone-320 available here:
https://developer.arm.com/documentation/109760/0000/SSE-320-FVP/SSE-320-FVP-memory-map
the non-secure world alias of DDR4 starts at 0x6000_0000 and
the secure world alias starts at 0x7000_0000.

Previously, the shared DDR4 node in mps4_common.dtsi listed multiple
regions, but Zephyr generated a linker memory region **only** for the
first address (0x6000_0000). This broke samples like `tflm_ethosu`,
on Corstone-320, which expect DDR4 memory region to start at 0x7000_0000
for secure variants of the MPS4 board.

Moving DDR4 definitions to per-board dts files ensures Zephyr creates
correct memory regions for each variant.
This also makes all the DDR4 regions available for applications to use
not just the first (applications would otherwise have to use some linker
magic to make those regions available in linker script).

Signed-off-by: Sudan Landge <[email protected]>

Use TF-M that has cherry-picked commits from upstream to fix compiler
warnings for MPS4.

Signed-off-by: Sudan Landge <[email protected]>